[AK1541] m s1043 - e - 0 5 1 20 13 / 03 AK1541 20 to 6 00mhz delta - sigma fractional - n frequency synthesizer 1. overview the AK1541 is a delta - sigma fractional - n pll (phase locked loop) frequency synthesizer with a frequency switching function, covering a wide range of frequencies from 20 to 600mhz. this product consists of an 18 - bit delta - sigma modulator, a low - noise phase frequency comparator, a highly accurate charge pump, a reference divider and a dual - modul e prescaler (p/p+1). an excellent pll can be achieved by combining this synthes izer with the external loop filter and vco (voltage controlled oscillator). the a ccess to the registers is controlled via a three - line s serial interface. the operat ing supply voltage is from 2.7 to 5.5v; and the c harge pump and serial interface can be driv en by individual supply voltages. 2. features ? delta - sigma fractional - n frequency synthesizer providing shorter lockup time, lower phase noise and low spurious performance ? operating frequency: 20 to 600mhz ? on - chip charge pump for fast lockup ? programmable charge pump current: in a normal operating scheme, the charge pump current can be set in 16 steps, in the range from 10.6 to 168.9ua. in a fast lockup scheme, the charge pump current can be set in 8 steps, in the range from 0.84 to 2.32ma. ? supply voltage: 2.7 to 5.5 v (pvdd and cpvdd pins) ? separate power supply for the charge pump: pvdd to 5.5v (cpvdd pin) ? on - chip power - saving features ? on - chip pll lock detect feature: direct output to the pfd ( p hase f requency d etector) or digital filtering output can be selected. ? very l ow consumption current: 3.4ma typ. (excluding a charge pump current) ? package: 24pin qfn ( 0.5mm pitch, 4mm ? 4mm ? 0.7 mm) ? operating temperature: - 40c to 85c
[AK1541] m s1043 - e - 0 5 2 20 13 / 03 table of contents 1. overview ________________________________ ________________________________ ___________ 1 2. features ________________________________ ________________________________ ___________ 1 3. block diagram ________________________________ ________________________________ ______ 3 4. pin functi onal description ________________________________ ____________________________ 4 5. absolute maximum ratings ________________________________ ___________________________ 6 6. recommended operating range ________________________________ _______________________ 6 7. electrical characteristics ________________________________ ______________________________ 7 8. block functional descriptions ________________________________ ________________________ 11 9. register map ________________________________ ________________________________ _______ 19 10. register functional description ________________________________ _______________________ 20 11. ic interface schematic ________________________________ _______________________________ 26 12. recommended co nnection schematic for off - chip components ___________________________ 28 13. power - up sequence ________________________________ ________________________________ _ 30 14. typical evaluation board schematic ________________________________ ___________________ 32 15. block diagram by power supply ________________________________ _______________________ 33 16. outer dimensions ________________________________ ________________________________ ___ 34 17. marking ________________________________ ________________________________ ___________ 35 in this specification (draft version), the following notations are used for specific signal and register names: [name]: pin name : register group name (address name) { name}: register bit name
[AK1541] m s1043 - e - 0 5 3 20 13 / 03 3. block diagram fig. 1 block diagram charge pump 2 (for fast lock up) cp cpz phase freqency detector refin + - prescaler 4/5,8/9,16/17 pulse swallow counter lock detect rfinp rfinn swin cpvdd cpvss pvdd vref2 vref1 dvss pvss ld ? 18bit clk data le register 24bit n divider fast counter 13bit pdn1 test2 test1 ldo test3 pdn2 test4 r counter 8bit bias charge pump 1
[AK1541] m s1043 - e - 0 5 4 20 13 / 03 4. pin functional description table 1 pin function no. n ame i/o pin functions power down remarks 1 cpvdd p power supply for charge pump 2 test4 di test pin 4 inter nal pull - down, schmidt trigger input 3 test1 di test pin 1 internal pull - down, schmidt trigger input 4 le di load enable schmidt trigger input 5 data di serial data input schmidt trigger input 6 clk di serial clock schmidt trigger input 7 ld do lock detect low 8 pdn2 di power down pin for pll schmidt trigger input 9 pdn1 di power down signal for ldo schmidt trigger input 10 refin ai reference input 11 test2 di test pin 2 internal pull - down, schmidt trigger input 12 test3 di test pin 3 internal pull - down, schmidt trigger input 13 vref1 aio connect to ldo reference voltage capacitor low 14 dvss g digital ground pin 15 vref2 aio connect to ldo reference voltage capacitor low 16 rfinn ai prescaler input 17 rfinp ai presca ler input 18 pvdd p power supply for peripherals 19 bias aio resistance pin for setting charge pump output current 20 pvss g ground pin for peripherals 21 cp ao charge pump output hi - z 22 cpz aio connect to the loop filter capacitor notes 1) & 2) 23 swin ai connect to resistance pin for fast lockup notes 1) & 2) 24 cpvss g ground pin for charge pump note 1) for detailed functional descriptions, see the section charge pump and loop filter in 8 . block functional description below. note 2) the input voltage from the [ cpz ] pin is used in the internal circuit. the [ cpz ] pin must not be open even when the fast lockup feature is unused. for the output destination from the [ cpz ] pin, see p.1 2 fig.5 loop
[AK1541] m s1043 - e - 0 5 5 20 13 / 03 filter schematic. the [ swin ] pin could be open even when the first lockup feature is not used. note 3) power down refers to the state where [ pdn1 ] = [ pdn2 ] =low after power - on. ai: analog input pin ao: analog output pin aio: analog i/o pin di: digital input pin do: digital output pin p: power supply pin g: ground pin fig. 2 package pin layout 1 2 3 4 5 6 7 8 9 10 15 14 13 12 11 20 19 18 17 16 top view 23 24 22 21 cpvdd test4 test1 data le clk ld pdn2 pdn1 refin test2 test3 vref1 dvss vref2 rfinn rfinp pvdd bias pvss cp cpz swin cpvss
[AK1541] m s1043 - e - 0 5 6 20 13 / 03 5. absolute maximum ratings table 2 absolute maximum ratings parameter symbol min. max. unit remarks supply voltage vdd1 - 0.3 6.5 v note 1 ) applied to the [ pvdd ] pin vdd2 - 0.3 6.5 v note 1 ) applied to [ cpvdd ] pin ground level vss1 0 0 v voltage ground level applied to the [ pvss ] pin vss2 0 0 v voltage ground level applied t o the [ cpvss ] pin vss3 0 0 v voltage ground level applied to the [ dvss ] pin analog input voltage vain1 vss1 - 0.3 vdd1+0.3 v notes 1 ) & 2 ) vain2 vss2 - 0.3 vdd2+0.3 v notes 1 ) & 3 ) digital input voltage vdin vss3 - 0.3 vdd1+0.3 v notes 1 ) & 4 ) input cur rent iin - 10 10 ma storage temperature tstg - 55 125 c note 1) 0v reference for all voltages. note 2) applied to the [ refin ] , [ rfinn ] and [ rfinp ] pins. note 3) applied to the [ cpz ] and [ swin ] pins. note 4) applied to the [ clk ] , [ data ] , [ le ] , [ pdn1 ] , [ pdn2 ] , [ test1 ] , [ test2 ] , [ test3 ] and [ test4 ] pins. exceeding these maximum ratings may result in damage to the AK1541. normal operation is not guaranteed at these extremes. 6. recommended operating range table 3 recommended operating range parameter symbol min. typ. max. unit remarks operating temperature ta - 40 85 ? c supply voltage vdd1 2.7 3.3 5.5 v applied to the [ pvdd ] pin vdd2 vdd1 5.0 5.5 v applied to the [ cpvdd ] pin note 1) vdd1 and vdd2 can be driven individually within the recommended operating range. the specifications are applicable within the recommended operating range (supply voltage/operating temperature).
[AK1541] m s1043 - e - 0 5 7 20 13 / 03 7. electrical characteristics 1. digital dc characteristics table 4 digital dc characteristics parameter symbol conditions min. typ. max. unit remarks high level input voltage vih 0.8vdd1 v note 1 ) low level input voltage vil 0.2vdd1 v note 1 ) high level input current 1 iih1 vih = vdd1=5.5v - 1 1 a note 2 ) high level input current 2 iih2 vih = vdd1=5.5v 27 55 110 a note 3 ) low level input current iil vil = 0v, vdd1=5.5v - 1 1 a note 1 ) high level output voltage voh ioh = - 500 ? a vdd1 - 0.4 v note 4 ) low level output voltage vol iol = 500 ? a 0.4 v note 4 ) note 1) applied to the [ clk ] , [ data ] , [ le ] , [ pdn1 ] , [ pdn2 ] , [ test1 ] , [ test2 ] , [ test3 ] and [ test4 ] pins. note 2) applied to the [ clk ] , [ data ] , [ le ] , [ pdn1 ] and [ pdn 2 ] pins. note 3) applied to the [ test1 ] , [ tes t2 ] , [ test3 ] and [ test4 ] pins. note 4) applied to the [ ld ] pin.
[AK1541] m s1043 - e - 0 5 8 20 13 / 03 2. serial interface timing fig. 3 serial interface timing table 5 serial interface timing parameter symbol mi n. typ. max. unit remarks clock l level hold time tcl 40 ns clock h level hold time tch 40 ns clock setup time tcsu 20 ns data setup time tsu 20 ns data hold time thd 20 ns le setup time tlesu 20 ns le pulse width tle 40 ns no te 1) le pin has to be set low after register data setting completed. if le pin keeps high with clk operation, the register may not be guarantee d proper setting. note 2) while le pin is setting low , 24 iteration clocks have to be set with clk pin. if 25 or larger clocks are set, the last 24 clocks synchronized data are valid. le (input) clk (input) data (input) tsu thd tcsu d19 d18 d0 a0 a1 a2 a3 tch t cl tlesu tle d19
[AK1541] m s1043 - e - 0 5 9 20 13 / 03 3. analog circuit characteristics the resistance of 27 k? is connected to the [ bias ] pin, vdd1 = 2.7 to 5.5v, vdd2=vdd1 to 5.5v, C 40c ta 85c parameter min. typ. max. unit remarks rf characteristics input sensitivity - 15 +5 dbm input frequency 100mhz 20mh input frequency < 100mhz refin characteristics input sensitivity 0.4 2 vpp input frequency 5 40 mhz maximum allowable prescaler output frequency 75 mhz phase detector phase detector frequency 3 mh z charge pump charge pump 1 maximum value 168.9 a charge pump 1 minimum value 10.6 a charge pump 2 maximum value 2.32 ma charge pump 2 minimum value 0.84 ma icp tri - state leak current 1 na 0.5 vcpo vdd2 0.5 vcpo vdd2 others vref1,2 rise time 50 s current consumption idd1 10 a [pdn1]= see fi g. 4 charge pump characteristics - voltage vs. current: icp vs. vcpo: [{1/2(|i1| - |i2|)}/{1/2(|i1|+|i2|)}]100 [%] note 3 ) [pdn1]= high , [pdn2]= high , the total current consumption = idd2 + idd3 + charge pump setting note 4 ) in the shipment test, the exposed pad on the center of the back of the package is connected to ground.
[AK1541] m s1043 - e - 0 5 10 20 13 / 03 resistance connected to the bias pin for sett ing charge pump output current parameter min. typ. max. unit remarks bias resistance 22 27 33 k? fig. 4 charge pump characteristics - voltage vs. current isink isource vcpo icp vdd2 - 0.5 vdd2/2 0.5 i1 i1 i2 i2
[AK1541] m s1043 - e - 0 5 11 20 13 / 03 8. block functional descriptions 1. frequency setu p the AK1541 is a fractional - n type synthesizer that takes 2 18 as the denominator, which calculates the integer and numerator to be set using the following formulas: frequency setting = ref frequency x (integer + numerator / 2 18 ) integer = round (target fr equency / f pfd ) numerator = round {(target frequency C pfd ) / ( f pfd / 2 18 )} note) round: rou nded off to the nearest value f pfd : phase frequency detector comparative frequency ([refin] pin input frequency/r divider ratio) ? calculation examples e xample 1) the numerator is positive when the target frequency is 465.0375mhz and the phase frequency detector comparative frequency is 1mhz. integer = 465.0375mhz / 1mhz = 465.0375 it is rounded off to 465 (decimal) = 1d1 (hexadecimal) = 1 1101 0001 (bina ry) numerator = (465.0375mhz - 465 x 1mhz) / (1mhz / 2 18 ) = 9830.4 it is rounded off to 9830 (decimal) = 2666 (hexadecimal) = 10 0110 0110 0110 (binary) frequency setting =1mhz x (465 + 9830 / 2 18 ) = 465.0374985mhz (in this case the error between the calc ulated frequency and the target frequency is 1.5hz.) example 2) the numerator is negative when the target frequency is 468.550mhz and the phase frequency detector comparative frequency is 1mhz. integer = 468.550mhz / 1mhz = 468.550 it is rounded off to 4 69 (decimal) = 1d5 (hexadecimal) = 1 1101 0101 (binary) numerator = (468.550mhz - 465 x 1mhz) / (1mhz / 2 18 ) = - 117964.8 it is rounded off to - 117965 (decimal), which is deduced from 2 18 to be converted into binary for 2's complementary expression. 2 18 - 1 17965 (decimal) = 144179 (decimal) = 23333 (hexadecimal) = 10 0011 0011 0011 0011 (binary) frequency setting =1mhz x (469 + ( - 117965/2 18 )) = 468.5499992mhz (in this case the error between the calculated frequency and the target frequency is 0.8hz.) ? calcu lation of 2s complement representation 1) positive number: binary expression (unmanipulated) exp. 100 (decimal) = 64 (hexadecimal) = 110 0100 (binary) 2) negative number: 2 18 minus this number in binary expression exp. C 100 (decimal) 2 18 - 100 = 2620 44 (decimal) = 3ff9c (hexadecimal) = 11 1111 1111 1001 1100 (binary)
[AK1541] m s1043 - e - 0 5 12 20 13 / 03 2. charge pump and loop filter the AK1541 has two charge pumps; charge pump 1 for normal operation and charge pump 2 for fast lockup. the internal timer is used to switch those two char ge pumps to achieve a fast lock pll. the loop filter is external and connected to [ cp ] , [ swin ] and [ cpz ] pins. the [ cpz ] pin should be connected to the r2 and c2 , which are intermediate nodes, even if the fast lockup is not used. therefore, r2 must be con nected to the [ cp ] pin, while c2 must be connected to the ground. r2 and r2 are connected in parallel with internal switch in fast lockup. these r2 and r2 parallel resistance value is required for calculating loop bandwidth and phase margin in fast locku p. fig. 5 loop filter schematic c2 phase detector up down timer vco loop filter c1 c3 r2 r2' r3 cp cpz swin
[AK1541] m s1043 - e - 0 5 13 20 13 / 03 3. fast lockup mode setting d[16] = { fasten } in to 1 enables the fast lock up mode for the AK1541. changing a frequency setting ( the frequency is changed at the rising edge of [ le ] when and are accessed. ) or [pdn2] pin is set low to high with {fasten}=1 enables the fast lockup mode. the loop filter switch turns on during the timer period specified by the counter value in d[12:0] = { fast [12:0] } in , and the charge pump for the fast lockup mode (charge pump 2) is enabled. after the timer period elapsed, the loop filter switch turns off . t he charge pump for normal operation (charge pump 1) is enabled . . d[12:0] = { fast[12:0] } in is used to set the timer period for this mode. the following formula is used to calculate the time period: phase detector frequency cycle x counter value set in { fast[12:0] } the charge pump current can be changed with the register setting in 1 6 steps in normal operation (charge pump 1) and 8 steps in the fast lockup operation (charge pump 2). the charge pump current for normal operation (charge pump 1) is determined by the setting in { cp1[3:0] } , which is a 4 - bit address of d[18:15] in , and a value of the resistance connected to the [ bias ] pin (19) . the following formula s show the relationship between the resistance value, the register setting and the electric current value. charge pump 1 minimum current (cp1_min) = 0.285 / resistance connected to the [ bias ] pin (19) charge pump 1 current = cp1_min x ( charge pump 1 setting + 1) the charge pump current for the fast lockup mode operation (charge pump 2 current) is determined by the setting in { cp2[2:0] } , which is a 3 - bit address of d[15 :13] in , and a value of the resistance connected to the bias pin the following formula show the relationship between the resistance value, the register setting and the electric current value. charge pump 2 minimum current (cp2_min) = 5.7 / resi stance connected to the [ bias ] pin charge pump 2 minimum current (cp2_min) = cp2_min x ( charge pump 2 setting + 4) the allowed range value for the resistance ( connected to the [ bias ] pin (19)) i s from 33 to 22 [k] for both normal and fast lockup mode operations. for details of current settings, see 10 . register functional description. fig. 6 timing chart for fast lockup mode fast lockup mode charge pump 2 on normal normal charge pump 1 off charge pump 1 off first lockup time specified by the timer operation mode charge pump l op filter switch the frequency is changed or [pdn2] pin is set low to high when d[16]={fsten} in < address4 > is set to 1 .
[AK1541] m s1043 - e - 0 5 14 20 13 / 03 4. lock detect (ld) signal in the AK1541, lock detect output can be selected by d[11] = { ld } in . when d[11] is set to 1" t he phase detector outputs provides a phase detection status as an analog level (comparison result) . th is is called analog lock detect . when d[11] is set to 0, the lock detect signal is output a ccording to the on - chip logic. this is called digital lock detect. 4.1 analog lock detect in analog lock detect, the phase detector output comes from the [ ld ] pin. fig. 7 analog lock detect operations reference clock pfd clock vco divide clock phase detector output ld output ldcksel=1
[AK1541] m s1043 - e - 0 5 15 20 13 / 03 4.2 digital lock detect the accuracy of the phase detect is set by {ldcksel[1:0]} . {ldcksel[1:0]} is set to 0: t = refin cycle {ldcksel[1:0]} is set to 1: t = refin cycle 2 (this cannot be used for the reference dividing ratio 5.) {ldcksel[1:0]} is set to 2: t = refin cycle 3 (this cannot be used for the reference dividing ratio 6.) in the digital lock detect, the [ld] pin outputs is low every time when the frequency is set. and the [ ld ] pin outputs is h igh (which mea ns the locked state) when a phase error smaller than t is detected for 63 times consecutively. if the phase error is larger than t is detected for n times consecutively then the [ld] pin outputs is high and then the [ld] pin outputs is low (which means the unlocked state). since the AK1541 is a delta - sigma fractional - n type, a phase error up to 7 times larger than the vco period frequency may occur in the phase detector. therefore the {ldcksel[1:0]} setting should be large enough to cover the amplitude of the delta - sigma fractional frequency. however, if the vco frequency does not satisfy either of the following formula, the digital lock detect cannot be used. in such case, the analog lock detect should be used. { dith } = d14 in is set to 1: vco frequency > [ refin ] pin input frequency / [ {ldcksel[1:0]} setting + 1] x 7 { dith } = d14 in is set to 0: vco frequency > [ refin ] pin input frequency / [ {ldcksel[1:0]} setting + 1] x 4 example 1) if [ refin ] pin input frequency = 33.6mhz, { dit h } = 1, {ldcksel[1:0]} = 2 , 33.6mhz / (2+1) x 7 = 78.4mhz as a result, the digital lock detect cannot be used if the vco frequency is equivalent to or smaller than 78.4mhz. example 2) if [ refin ] pin input frequency = 33.6mhz, { dith } = 0, {ldcksel[1:0]} = 1, 33.6mhz / (1+1) x 4 = 67.2mhz as a result, the digital lock detect cannot be used if the vco frequency is equivalent to or smaller than 67.2mhz.
[AK1541] m s1043 - e - 0 5 16 20 13 / 03 ? setup example dith = d14 in is set to 1: available unavailable vco frequency at the lower limit 180mhz 70mhz [ refin ] pin input frequency 12.8mhz 32mhz {ldcksel[1:0]} 0 2 formula 180mhz > 12.8/ ( 0+1 ) x 7 = 89.6mhz 70mhz < 32/ ( 2+1 ) x 7 = 74.67mhz dith = d14 in is set to 0: available unavailable vco frequency at the lower limit 1 80mhz 60mhz [ refin ] pin input frequency 12.8mhz 32mhz {ldcksel[1:0]} 0 1 formula 180mhz > 12.8/ ( 0+1 ) x 4 = 51.2mhz 60mhz < 32/ ( 1+1 ) x 4 = 64mhz fig. 8 digital lock detect operation in valid invalid reference clock pfd clock vco divide clock phase detector output valid valid valid invalid valid ldcksel=0
[AK1541] m s1043 - e - 0 5 17 20 13 / 03 fig. 9 transition flow chart: unlock state to lock state fig. 10 transition flow chart: lock state to unlock state phase error < t flag=flag+1 lock([ld]= hi gh ) unlock([ld]= low ) yes no flag>63 flag=0 yes no phase error > t yes flag=0 flag=flag+1 flag>63 no yes unlock([ld]= low ) no lock([ld]= high ) address2 write
[AK1541] m s1043 - e - 0 5 18 20 13 / 03 5. reference input the reference input can be set with a d ividing number in the range of 4 to 255 using {r[ 7 :0]} , which is a 8 - bit address in . a dividing number from 0 to 3 cannot be set. 6. prescaler and swallow counter the dual modular prescaler ( p/p + 1 ) and the swallow counter are used to provide a large dividing ratio. the prescaler is set by {pre[1:0]} , which is a 2 - bit address in . when {pre[1:0]} =00, p = 4 is selected and then an integer from 89 to 8191 can be set. when {pre[1:0]} =01, p = 8 is selected and then an integer from 201 to 16383 can be set. when {pre[1:0]} =10 or 11, p = 16 is selected and then an integer from 521 to 32767 can be set. for details of how to calculate an integer, see the section frequency setup in 8. block functional description. 7. power save mode the AK1541 can be operated in the power - down or power - save mode as necessary by using the external control pins [ pdn1 ] and [ pdn2 ] . power on see 13 . power - up sequence. it is necessary to bring [pdn1] t o high first, then [pdn2]. bringing [pdn1] and [pdn2] to high simultaneously is prohibited . normal operation pin name state pdn1 pdn2 is set to high . the charge pump is in the hi - z state. note 2) register settings are maintained when [ pdn2 ] is set to low during normal operation.
[AK1541] m s1043 - e - 0 5 19 20 13 / 03 9. register map name d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address num 0 0 num [17] num [16] num [15] num [14] num [13] num [12] num [11] num [10] num [9] num [8] num [7] num [6] num [5] num [4] num [3] num [2] num [1] num [0] 0x01 int 0 cp1 [3] cp1 [2] cp1 [1] cp1 [0] int [14] int [13] int [12] int [11] int [10] int [9] int [8] int [7] int [6] int [5] int [4] int [3] int [2] int [1] int [0] 0x02 div 0 0 0 0 cp hiz di th ldck sel[1] ldck sel[0] ld cp pola pre [1] pre [0] r [7] r [6] r [5] r [4] r [3] r [2] r [1] r [0] 0x03 c p _fast 0 0 0 fast en cp2 [2] cp2 [1] cp2 [0] fast [12] fast [11] fast [10] fast [9] fast [8] fast [7] fast [6] fast [5] fast [4] fast [3] fast [2] fast [1] fast [0] 0x04 note 1) writing into address 0x01 is enabled when writing into address 0x02 is performed. be sure to write into address 0x01 first and then address 0x02. note 2) t he initial register values are not defined. therefore , even after [ pdn1 ] is set to high , each bit value remains undefined. in order to set all register values , it is required to write the data in all addresses of the register . name data address num d 19 to d0 0 0 0 1 int 0 0 1 0 div 0 0 1 1 cp_fast 0 1 0 0
[AK1541] m s1043 - e - 0 5 20 20 13 / 03 10. register functional description < address 1 : num > d19 d18 d[17:0] address 0 0 num[17:0] 0001 note) writing into address 0x01 is enabled when writing into address 0x02 is performed. num[17:0] : set the numerator in 2s complementary representation. < address 2 : int > d19 d[18:15] d[14:0] address 0 cp1[3:0] int[14:0] 0010 cp1[3:0] : set s th e current value for the charge pump in normal operation (charge pump 1). the minimum current value for charge pump 1 (cp1_min) is determined by the following formula: cp1_min = 0.285 / resistance connected to the [ bias ] pin charge pump 1 current = c p1_min x (cp1 setting + 1) charge pump 1 current [ a] cp1[3:0] 22 k? 27 k? 33k? 0000 13.0 10.6 8.6 0001 25.9 21.1 17.3 0010 38.9 31.7 25.9 0011 51.8 42.2 34.5 0100 64.8 52.8 43.2 0101 77.7 63.3 51.8 0110 90.7 73.9 60.5 0111 103.6 84.4 69.1 1000 1 16.6 95.0 77.7 1001 129.5 105.6 86.4 1010 142.5 116.1 95.0 1011 155.5 126.7 103.6 1100 168.4 137.2 112.3 1101 181.4 147.8 120.9 1110 194.3 158.3 129.5 1111 207.3 168.9 138.2 int[14:0] : set s the integer.
[AK1541] m s1043 - e - 0 5 21 20 13 / 03 < address 3 : div > d19 d18 d17 d16 d15 d14 d[13:12] d11 d10 d[9:8] d[7:0] addres s 0 0 0 0 cphi z dith ldcksel[1:0] ld cppola pre[1:0 ] r [7:0] 0011 cphiz: selects normal or tri - state for the cp1/cp2 output. d15 function remarks 0 charge pumps are activated. use this setting for normal operation. 1 tri - state note 1 ) note 1) the charge pump output is put in the high - impedance (hi - z) state. dith: selects dithering on or off for a delta - sigma circuit. d14 function remarks 0 dith off 1 dith on recommended it is used to control the turning o n or o ff dithering to cancel cyclical noise. in normal operation, 1= dith on is recommended. ldcksel[1:0] : sets a phase error value for lock detect. d13 d12 function remarks 0 0 1 cycle of the refin clock 0 1 2 cycles of the refin clock 1 0 3 cyc les of the refin clock 1 1 prohibited for detailed functional descriptions, see the section lock detect (ld) signal in 8 . block functional description. ld: selects analog or digital for the lock detect . d11 function remarks 0 digital lock detect 1 analog lock detect for detailed functional descriptions, see the section lock detect (ld) signal in 8 . block functional description.
[AK1541] m s1043 - e - 0 5 22 20 13 / 03 cppola: selects posi tive or negative output polarity for charge pump 1 and charge pump 2. d10 function remarks 0 positive 1 negative fig. 11 charge pump slope polarity high high charge pump output voltage negati ve positive low low vco frequency
[AK1541] m s1043 - e - 0 5 23 20 13 / 03 pre[1:0] : selects a dividing ratio for the pr escaler. d9 d8 function remarks 0 0 p=4 0 1 p=8 1 0 p=16 1 1 p=16 r[7:0]: sets a dividing ratio for the reference clock. this can be set in the range from 4 (4 divisions) to 255 (255 divisions). 0, 1, 2 or 3 cannot be set. d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 1 1 prohibited 0 0 0 0 0 0 1 0 2 prohibited 0 0 0 0 0 0 1 1 3 prohibited data 1 1 1 1 1 1 0 1 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255
[AK1541] m s1043 - e - 0 5 24 20 13 / 03 < address 4 : cp_fast > d19 d18 d17 d16 d[15:13] d[12:0] addres s 0 0 0 fasten cp2[2:0] fast[12:0] 0100 fasten: enables or disables the fast lockup mode. d16 function remarks 0 the switchover settings specified in cp2[2:0] and fast[12:0] are disabled. 1 the switchover settings specified i n cp2[2:0] and fast[12:0] are enabled. cp2[2:0]: sets the current value for the charge pump for the fast lockup mode (charge pump 2). the minimum charge pump 2 current (cp2_min) is determined by the following formula: cp2_min = 5.7 / resistance co nnected to the [ bias ] pin charge pump 2 minimum current (cp2_min) = cp2_min x (cp2 setting + 4) charge pump 2 current [ma] cp2[2:0] 22 k? 27 k? 33k? 000 1.04 0.84 0.69 001 1.30 1.06 0.86 010 1.55 1.27 1.04 011 1.81 1.48 1.21 100 2.07 1.69 1.38 101 2.33 1.90 1.55 110 2.59 2.11 1.73 111 2.85 2.32 1.90
[AK1541] m s1043 - e - 0 5 25 20 13 / 03 fast[12:0] : sets the fast counter value. a decimal number from 1 to 8191 can be set. this counter value is used to set the time period during which the charge pump for the fast lockup mode is on. the charge pump for the fast lockup mode is turned off after the time period calculated by [this count value x phase detector frequency cycle ]. 0 cannot be set. d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function remarks 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 dec 0 0 0 0 0 0 0 0 0 0 0 1 0 2 dec data 1 1 1 1 1 1 1 1 1 1 1 0 1 8189 dec 1 1 1 1 1 1 1 1 1 1 1 1 0 8190 dec 1 1 1 1 1 1 1 1 1 1 1 1 1 8191 dec
[AK1541] m s1043 - e - 0 5 26 20 13 / 03 11. ic interface schematic no. n ame i/o r0( ? ) cur( a) function 4 le i 300 digital input pins 5 data i 300 6 clk i 300 8 pdn2 i 300 9 pdn1 i 300 2 test4 i 3 00 digital input pins pull - down 3 test1 i 300 11 test2 i 300 12 test3 i 300 7 ld o digital output pin 10 refin i 300 analog input pin 13 vref1 io 300 analo g i/o pin 15 vref2 io 300 19 bias io 300 22 cpz io 300 r0 r0 100k r0 r0
[AK1541] m s1043 - e - 0 5 27 20 13 / 03 no. n ame i/o r0( ? ) cur( a) function 23 swin i analog input pin 21 cp o analog output pin 16 rfinn i 12k 20 a analog input pin ( rf signal input ) 17 rfinp i 12k 20 a r0
[AK1541] m s1043 - e - 0 5 28 20 13 / 03 12. recommended connection schematic for off - chip component s 1. pvdd , cpvdd 2. vref1 , vref2 3. test [1,2,3, 4] 10 ? f pvdd cpvdd 100pf 100pf 0.01 ? f 10 ? f lsi 0.01 ? f c1 vref1 vref2 lsi c1 : 220nf 10% c 2 : 220nf 10% vref 2 vref2 c 2 test [ 1,2,3,4 ] lsi
[AK1541] m s1043 - e - 0 5 29 20 13 / 03 4. refin 5. rfinp , rfinn 6. bias ref in c lsi c : 100pf 10 % lsi rfinp vco output rfinn see the typical evaluation board schematic for element values. lsi bias r : 22 to 33k ? r
[AK1541] m s1043 - e - 0 5 30 20 13 / 03 13. power - up sequence 1. pow er - up sequence (recommended ) fig. 12 recommended power sequence note 1) the initial register values are not defined. therefore, even after [pdn1] is set to high , each bit value remains undefined. in order to set all register values, it is required to write the data in all addresses of the register. pvdd,cpvdd write to t he register on - chip ldo ( 1.8v ) pdn2(pll) internal resiter values are set cp output 0v 1.8v 50 ?
[AK1541] m s1043 - e - 0 5 31 20 13 / 03 2. power - up sequence fig. 13 power sequence pvdd,cpvdd write to register on - chip ldo ( 1.8v ) pdn2(pll) cp 0v 50 ? s hiz pdn1 refin d on t care input output (*1) registers can be written after more than 50 ? s from the [pdn1] is set to high here [pdn1] is set to high after or at the same time as power - up. 1.8v refin must be input before setting [pdn2] to high *1 cp output is not defined before writing the data in all addresses of the register. after writing them, cp output can be control led by register. h or l
[AK1541] m s1043 - e - 0 5 32 20 13 / 03 14. typical evaluation board schematic fig. 14 typical evaluation board schematic the input voltage from the [ cpz ] pin is used in the internal circuit. the [ cpz ] pin must not be open even when the fast lockup feature is unused. for the output destination from the [ cpz ] pin, see p.12 fig.5 loop filter schematic. the [ swin ] pin could be open even when the first lockup feature is not used. r2 and r2 are connected in parallel with internal switch in fast lockup. these r2 and r2 parallel resistance value is required for calculating loop bandwidth and phase margin in fast lockup. a n on resistance value of the internal switch is 150 ? for reference. c2 AK1541 loop filter c1 c3 r2 r2' r3 cp cpz swin rfout 51 100pf rfinn vco bias rfinp 100pf 27k refin vref1 vref2 220nf 220n f 100pf 100pf 18 18 18
[AK1541] m s1043 - e - 0 5 33 20 13 / 03 15. block diagram by power supply fig. 15 block diagram by power supply
[AK1541] m s1043 - e - 0 5 34 20 13 / 03 16. outer dimensions fig. 16 outer dimensions note) it is recommended to connect the ex posed pad ( the center of the back of the package ) to ground, although it will not make any impact on the electrical characteristics if the pad is open. 0.05 s 2.40 2.40 0.400.10 c0.30 1 13 18 19 24 12 7 4.000.10 4.000.10 0.220.05 a 2.00 b 2.00 s part a 0.5 0.75max 0.70 0.05max 6 0.05 m s a b 0.00
[AK1541] m s1043 - e - 0 5 35 20 13 / 03 17. marking (a) style : qfn (b) number of pins : 24 (c) 1 pin marking: : (d) product number : 154 1 (e) d ate code : ywwl (4 digits) y : lower 1 d igit of calendar year (year 20 11 1 , 20 12 2 ...) ww : week l : lot identification, given to each product lot which is made in a week ? lot id is given in alphabetical order (a, b, c) . fig. 17 marking ywwl (e) (c) 1541 (d)
[AK1541] m s1043 - e - 0 5 36 20 13 / 03 important notice ? these products and their specifications are subject to change without notice. when you consider any use or application of these products , please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributor s as to current status of the products. ? descriptions of external ci r cuits, application circuits, software and other related info r mation contained in this document are provided o nly to illustrate the operation and application examples of the semiconductor products . you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipment s . akm assumes no responsibility for any loss e s incurr e d by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, curre ncy exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the respon sibility of the buyer or distributor of akm product s, who distributes, disposes of, or otherwise places the product with a third party , to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
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